Field-effect transistors are employed in many areas of electronics, in particular as switch elements or as storage elements of an integrated circuit.
New types of transistors are being developed and used particularly in the course of the ever increasing requirements made of mass storage devices.
In order to increase the storage density of a semiconductor memory, Eitan, B, Pavan, P, Bloom, I, Aloni, E, Frommer, A, Fiñzi, D (2000) “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell” IEEE Electron Device Letters 21(11): 543-545, discloses using a so-called ONO field-effect transistor in order to store two bits of information therein. In the case of the field-effect transistor disclosed in Eitan et al., an ONO layer sequence having a silicon nitride layer between two silicon oxide layers is provided above the channel region between the two source/drain regions. The electrical transistor properties of the ONO field-effect transistor can be characteristically influenced by introducing charge carriers into the silicon nitride layer of the ONO layer sequence. A quantity of charge that codes the information to be stored is stored in the boundary regions between a respective one of the two source/drain regions and the ONO layer sequence using the tunnel effect. An item of stored information can be read out on account of the altered transistor properties (e.g. sign or intensity of the shift in the value of the threshold voltage).
Hanafi, H I, Tiwari, S, Khan, I (1996) “Fast and Long Retention-Time Nano-Crystal Memory” IEEE Transaction on Electron Devices 43(9): 1553-1558, discloses forming nanocrystals made of germanium or silicon in a gate-insulating layer of a field-effect transistor and permanently introducing electrical charge carriers into said nanocrystals using the tunnel effect. The transistor properties of the field-effect transistor are thereby characteristically influenced, whereby the information that is stored in the field-effect transistor and is coded by means of the quantity of charge introduced in the nanocrystals can be read out as altered transistor properties.
An important branch of silicon microelectronics is so-called SOI technology (“Silicon-on-Insulator”). The principles of SOI technology are described in Widmann, D, Mader, H, Friedrich, H (1996) “Technologie hochintegrierter Schaltungen” [“Technology of large scale integrated circuits”], Chapter 8.4, Springer Verlag, Berlin, IBSN 3-540-59357-8, for example. SOI technology requires an SOI substrate constructed from a layer stack of silicon/silicon oxide/silicon, in which case the two silicon layers that surround the silicon oxide layer on both sides should if possible be monocrystalline.
A central problem of conventional integrated circuits is the deterioration in the electrical properties of MOS transistors with increasing structural fineness on account of effects such as the punch-through effect and the latch-up effect. These problems are alleviated with the use of SOI technology.
However, technological problems exist on the one hand in producing an insulated monocrystalline layer on a silicon oxide layer and on the other hand in integrating this process step into an overall process in the production of an integrated circuit.
A method for producing an SOI layer sequence is described in Homepage of the company Soitec (Feb. 12, 2002): http://www.soitec.com/unibond.htm, for example. In accordance with the Smart-Cut™ method described therein, which was developed by the company Soitec, hydrogen ions are implanted into an oxidized silicon substrate and form a buried, mechanically weakened stripping layer. Using a wafer bonding method, the silicon oxide layer can be fixed on a further silicon substrate. An SOI layer sequence is thereby obtained. After a suitable heat treatment method step, the SOI layer sequence arranged above the stripping layer and comprising a thin silicon layer, a silicon oxide layer and the silicon substrate at the surface may be stripped from the carrier wafer.
An important aspect in the formation of a field-effect transistor of an integrated circuit is the setting of the threshold voltage of the transistor. In conventional transistor generations, this is carried out by setting the doping of the channel region and by setting the gate work function, that is to say by selecting the material for the gate region. Furthermore, it is possible to form so-called pocket regions, that is to say specifically doped regions in the channel region, in order to influence the threshold voltage of a conventional transistor.
However, for technological reasons, the material for the gate region may be predetermined or the free material selection may be restricted, so that the material selection as a parameter for setting the threshold voltage of a field-effect transistor may be obviated. Furthermore, in SOI technology, usually a very thin silicon layer is provided above the silicon oxide layer, so that clearly a sufficient volume does not remain for forming pocket regions in thin-film SOI technology. Therefore, this parameter for setting the threshold voltage is also obviated in SOI technology.
Furthermore, setting the threshold voltage by doping the channel region has the disadvantage that, on account of technologically unavoidable inhomogeneity fluctuations in the charge carrier density in the channel region of different field-effect transistors of a circuit, the threshold voltage may also be subjected to fluctuation in an undesirable manner. Furthermore, the doping of the channel region leads to an increase in the number of scattering centers for charge carriers and therefore results in an undesirable increase in the nonreactive resistance.
Therefore, in thin-film SOI technology which is of interest technologically, setting the work function of the gate material remains at most as a parameter for setting the threshold voltage. However, the free selection of a material of the gate region may be restricted for technological reasons.
It must be emphasized that in single-gate SOI transistors or double-gate SOI transistors, a channel doping is often dispensed with in order to achieve a low nonreactive resistance and therefore a high on current, and in order to avoid fluctuations in the threshold voltage on account of a fluctuation in the dopant concentration. However, this often has the consequence that a transistor in the off state blocks sufficiently reliably only when, in the case of an n-channel transistor, use is made of a gate material with a work function that is at least as high as, for instance, the so-called “midgap” work function, and when the channel region is preferably fully depleted of free charge carriers.
As MOS field-effect transistors are structurally refined to an increasing extent, their operation leads to the amplification of negative effects such as e.g. threshold voltage drop, the punch-through effect, the latch-up effect, and to the parasitic capacitances between source/drain regions and the substrate that increase more than proportionally in relation to the reciprocal transistor size. SOI technology (SOI=silicon on insulator) represents a solution to the problems described above. In accordance with this technology, each component is produced in a thin silicon island that is electrically insulated from its surroundings. The absence of a connection between the silicon islands means that a latch-up effect cannot occur. Furthermore, short-channel effects are alleviated since the active function of the transistors is restricted to a thin silicon film.
So-called thick-film SOI substrates have principally been used hitherto. These substrates have a relatively thick layer of silicon which, after it has been produced, is converted by means of doping into a region that is partially depleted of electrical charge carriers (PD region=partially depleted region). These PD-SOI substrates are used for example in analog devices, in photodiode arrays and fast bipolar integrated circuits (ICs).
Thin-film SOI substrates, which have a thin layer of silicon, which layer, after it has been produced, is converted by means of weak doping into a region that is fully depleted of electrical charge carriers (FD region=fully depleted region), are used only to a small extent at the present time. These FD-SOI transistors have a high speed and also a low current consumption.
Owing to their high speed and the low current consumption, a rising proportion of FD-SOI substrates is expected in the future. The rising proportion of FD-SOI substrates will be accompanied by a need for substrates which contain both thin-film SOI regions and thick-film SOI regions on a substrate (mixed substrates) in order to be able to utilize the advantages of PD regions and FD regions on a common substrate. The thickness of the silicon layer or the degree of depletion of electrical charge carriers determines the threshold voltage of the transistor. For fast logic elements, e.g. transistors having different threshold voltages are integrated in a circuit. By way of example, transistors having approximately 6 different threshold voltages are found in an embedded flash element.
The threshold voltage of transistors applied on an FD-SOI substrate can preferably be set by way of the work function of the gate material of the transistor. In the case of a transistor applied on a PD-SOI substrate, the threshold voltage can be defined by way of a channel implantation as in the case of a bulk transistor. In this connection, the term bulk transistor refers to a transistor in the case of which the transistor is constructed by means of doping in the lightly doped region of the respectively complementary doping. By way of example, a p-type substrate is used for the realization of an NMOS transistor, into which substrate the NMOS transistor is realized directly.
Such mixed substrates have been produced hitherto by thinning a PD-SOI substrate, at the locations which are intended to form an FD region, to a residual thickness provided for an FD-SOI substrate. The thinning can be achieved by means of a local silicon etching of the PD-SOI layer. A further method for producing an FD layer on a PD-SOI substrate is a local oxidation of the PD-SOI layer with subsequent removal of the silicon oxide formed.
Furthermore, a mixed substrate can also be produced by a further silicon layer being formed onto an FD-SOI layer by means of selective epitaxy in a region of the FD-SOI layer, as a result of which a second region is formed in which the silicon layer has a larger thickness (PD-SOI region) than in the FD-SOI region. FIG. 1 illustrates a mixed substrate that has been produced in accordance with a method in accordance with the prior art.
FIG. 1 shows an SOI substrate 100 in accordance with the prior art, which has, on a silicon carrier substrate 101, a silicon oxide layer 102 and regions of a silicon semiconductor layer 103 which have different thicknesses. A first region 104 of the silicon semiconductor layer 103 has a smaller thickness of typically approximately 20 nm and is formed as a region that is fully depleted of charge carriers. A second region 105 of the silicon semiconductor layer 103 has a larger thickness of typically approximately 100 nm and is formed as a region that is partially depleted of charge carriers. Generally, the two regions 104, 105 of the semiconductor layer are formed by deposition of a thick silicon semiconductor layer which is subsequently etched back in the region that is later intended to be reformed into the first region 104 fully depleted of charge carriers. This method for producing a mixed substrate in accordance with the prior art gives rise to problems in the further processing of the mixed substrate as a result of the regions of different thickness 104 and 105.
The steps caused by the different thicknesses of the silicon layers constitute a problem in the case of a subsequent gate wiring across the boundaries of the different FD regions and PD regions.
A further problem is that, during the subsequent lithographic exposure of the surface, as a result of the limited focus depth of a stepper used for the exposure, problems can arise during the exposure across the boundaries present between in each case a PD region and an FD region.
Furthermore, the methods in which the semiconductor layer is etched back in regions or in which the semiconductor layer is oxidized exhibit the problem that it is difficult to exactly control the silicon thicknesses produced by means of the etching or oxidation.
JP 2000 306 993 A discloses the production of a multilayer substrate, in which a thin-film semiconductor active layer can be formed with a uniform thickness and the work effectiveness can be improved.
JP 06 110 4412 A discloses the production of a semiconductor device, in which simple formation steps are used in order to reduce production costs and in order to simplify the quality control.